The present invention relates to a MOS type semiconductor device, such as a MOS field-effect transistor (hereinafter referred to as xe2x80x9cMOSFETxe2x80x9d) or an insulated gate bipolar thyristor (hereinafter referred to as xe2x80x9cIGBTxe2x80x9d), wherein a plurality of source regions having gates of metal-oxide-semiconductor (MOS) structure are separately formed in a surface layer of a semiconductor substrate.
To produce MOSFET as one example of the MOS type semiconductor device, for example, p base regions are formed by diffusing impurities into selected areas of a surface layer of an n type semiconductor substrate such that pn junctions are exposed onto the surface of the substrate, and n source regions are similarly formed in surface layers of the p base regions. A gate electrode layer is then formed on an insulating film over surfaces of channel regions provided by surface layers of the p base regions each interposed between the adjacent n source region and the n type semiconductor substrate, and a source electrode is formed in contact with both of the p base regions and n source regions. A drain electrode is formed on the other surface of the n type semiconductor substrate. By applying a suitable voltage to the gate electrode, an inversion layer appears in each channel region, to reduce resistance between the drain electrode and the source electrode, and current is allowed to flow between the drain electrode and the source electrode through the inversion layer.
To produce IGBT as another example, an additional p type region is formed oil one side of the MOSFET where the drain electrode is formed. With the p type region thus added, the IGBT is capable of modulating the conductivity by utilizing injection of minority carriers from the p type region.
The MOS type semiconductor device as described above is widely used in a switching circuit because the device has low ON-state resistance and high switching speed, and is easy to be controlled by use of voltage.
In recent years, the MOS type semiconductor device used as a switching device in a switching circuit is more likely to receive surge voltage, which may be generated due to simplified configuration of the switching circuit from which snubbers are eliminated, for example, and reduction in the size of the semiconductor device. In a circuit in which inductive load current is to be cut off, for example, the voltage applied to the MOS type semiconductor device is increased due to energy stored in an inductor, and sometimes becomes even higher than power supply voltage. This excessive voltage stress may cause breakdown of the MOS type semiconductor device, and it has been thus desired to increase the breakdown voltage (avalanche current) of the semiconductor device.
As one method for improving the capability of the MOS type semiconductor device to withstand avalanche breakdown, a part of the p base region is formed with a larger diffusion depth. The increase in the diffusion depth, however, affects the ON-state resistance and other characteristics of the semiconductor device. For example, if the depth of a part of the p base region is changed from 5 xcexcm to 7 xcexcm in a certain MOSFET, the avalanche current increases by 25%, but at the same time the ON-state resistance increases by 15%. Thus, this method is not altogether desirable.
FIG. 11 is a cross-sectional view of MOSFET (as disclosed in U.S. Pat. No. 5,365,099) that employs another method for increasing the breakdown voltage.
An ordinary MOSFET is shown in the left-side portion of FIG. 11. In this MOSFET, an n drift layer 13 is superposed on an n+ drain layer 11, and a plurality of p base regions 14 and p+ contact regions 15 inside the regions 14 are formed in a surface layer of the n drift layer 13. Further, n source regions 16 are formed in surface layers of the p base regions 14. A gate electrode layer 18 made of polycrystalline silicon, for example, is formed on a gate oxide film 17 over portions of the p base regions 14 that are interposed between the n source regions 16 and an exposed face of the n drift layer 13. A source electrode 19 made of Al alloy is formed in contact with both the p base regions 14 (p+ contact regions 15) and the n source regions 16. The source electrode 19 extends over the gate electrode layer 18 such that these electrodes 18, 19 are insulated from each other by an interlayer insulating film 21 made of boron phosphorous silica glass (BPSG). A drain electrode 20 made of Alxe2x80x94Si alloy is formed on the rear surface of the n+ drain layer 11. A unit structure having n source region 16, source electrode 19 and other elements above and below the p base region 14 will be called a cell structure. The cell structure is often formed in polygonal or rectangular shape, and a multiplicity of such cell structures are arranged in parallel with each other in an actual MOSFET.
A means for increasing the avalanche current is illustrated in the right-side portion of FIG. 11. An n+ contact region 7 is formed in a surface layer of the n drift layer 13, and an auxiliary electrode 8 is formed in contact with the n+ contact region 7. An array of a plurality of pairs of Zener diodes 10 that are connected in series is provided on a relatively thick oxide film 9 on the surface of the n drift layer 13. Each pair of the Zener diodes are reversely connected to each other. The above auxiliary electrode 8 is connected to one end of the series Zener diode array 10, and an electrode taken out from the other end of the Zener diode array 10 is connected to the gate electrode layers 18 of the MOSFET.
In this structure, the auxiliary electrode 8 and drain electrode 20 are held at the same potential. When a voltage applied to the drain electrode 20 increases to be higher than a clamping voltage of the series Zener diode array 10, therefore, a difference between the high voltage and the clamping voltage is applied to the gate electrode layers 18 of the MOSFET, to turn on the MOSFET thereby to protect the device.
To provide the construction of FIG. 11, however, a window must be formed through the thick oxide film 9 so that the n+ contact region 7 is formed in the surface layer of the n drift layer 13, and the n+ contact region 7 must be given a sufficiently large area so as to assure reliable operations.
It is therefore an object of the present invention to provide a MOS type semiconductor device which has improved capability to withstand avalanche breakdown, and can be easily manufactured and operate with high reliability.
To accomplish the above object, there is provided a MOS type semiconductor apparatus, comprising: a first MOS type semiconductor device through which first current flows, and which includes a source electrode and a gate electrode; a second MOS type semiconductor device through which second current that is smaller than the first current flows, the second MOS type semiconductor device having substantially the same structure as the first MOS type semiconductor device, and including a source electrode and a gate electrode, the first MOS type semiconductor device and the second MOS type semiconductor device being provided on the same semiconductor substrate, and having a common drain electrode, the gate electrode of the second MOS type semiconductor device being connected to the common drain electrode, and a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device, each of the plurality of pairs of Zener diodes being reversely connected to each other.
In the apparatus constructed as described above, the second MOS type semiconductor device is turned on when an excessively high voltage is applied between the drain electrode and the gate electrode of the first MOS type semiconductor device. As a result, current flows from the second MOS type semiconductor device into the gate electrode of the first MOS type semiconductor device via the plurality of pairs of Zener diodes, thereby to turn on the first MOS type semiconductor device, whereby the MOS type semiconductor apparatus is protected against the excessively high voltage, and the breakdown voltage of the apparatus can be thus increased.
Preferably, a pair of Zener diodes are provided between the gate electrode and the source electrode of the first MOS type semiconductor device. In this arrangement, when an excessively high voltage is applied between the gate electrode and the source electrode, current due to the voltage may flow through the pair of Zener diodes that provide a bypass, and thus a thin gate insulating film and other elements of the MOS type semiconductor apparatus can be protected against such an excessively high voltage.
Also, resistance is preferably provided between the gate electrode and the source electrode of the first MOS type semiconductor device. In this case, the gate electrode of the first MOS type semiconductor device, when it floats due to disconnection, or the like, can be protected against noise voltage.
Where both of the first and second MOS type semiconductor devices are insulated gate bipolar transistors, which are conductivity modulation type devices, only a small area of the first MOS type semiconductor device is required to allow large current to flow through the device.
In one form of the MOS type semiconductor apparatus of the present invention, each of the first and second MOS type semiconductor devices comprises: first main surface and second main surface that face in opposite directions; a first conductivity type drift layer; a second conductivity type base region formed in a surface layer of the first conductivity type drift layer on the side of the first main surface; a first conductivity type source region that is spaced from the first conductivity type drift layer by the second conductivity type base region; a gate electrode layer formed on a gate insulating film over a surface of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer, a source electrode formed in contact with both of the first conductivity type source region and the second conductivity type base region; a drain layer formed on a surface of the first conductivity type drift layer on the side of the second main surface; a drain electrode formed on the second main surface in contact with a surface of the drain layer; and a gate electrode formed in contact with the gate electrode layer. The thus constructed first and second MOS type semiconductor devices provide a vertical, planar type MOS semiconductor apparatus which assures sufficiently high efficiency with which its semiconductor substrate is utilized, and which may be used in many applications as a power semiconductor apparatus.
In another form of the present invention, each of the first and second MOS type semiconductor devices comprises: first main surface and second main surface that face in opposite directions, a first conductivity type drift layer having a high resistivity; a second conductivity type base region formed in a surface layer of the first conductivity type drift layer on the side of the first main surface; a first conductivity type source region that is spaced from the first conductivity type drift layer by the second conductivity type base region; a trench formed in the first conductivity type drift layer such that the first conductivity type source region is exposed to an inner wall of the trench, the trench having a larger depth than the second conductivity type base region, a gate electrode layer formed in the trench with a gate insulating film filling a space between the gate electrode layer and the inner wall of the trench, a drain layer formed on a surface of the first conductivity type drift layer on the side of the second main surface; a drain electrode formed on the second main surface in contact with a surface of the drain layer, and a gate electrode formed in contact with the gate electrode layer. The thus constructed first and second MOS type semiconductor devices provide a vertical, trench-gate-type MOS semiconductor apparatus which assures a further improved efficiency with which the semiconductor substrate is utilized, and which can be used in many applications as a power semiconductor apparatus.
In a further form of the present invention, a thick field insulating film is disposed on the first main surface between the first MOS type semiconductor device and the second MOS type semiconductor device. A part of the gate electrode layer of the second MOS type semiconductor device extends over the field insulating film. The field insulating film includes a small-thickness portion which has a smaller thickness than that of the field insulating film, and which is formed between the first conductivity drift layer and the gate electrode layer of the second MOS type semiconductor device that are located around the second conductivity type base region of the second MOS type semiconductor device. In this arrangement, an inversion layer is prevented from appearing under the thick field insulating film, and current is prevented from flowing between the second conductivity type base regions of the first and second MOS type semiconductive devices.
If the small-thickness portion of the field insulating film has substantially the same thickness as the gate insulating film, this portion may be formed at the same time when the gate insulating film is formed, without making the manufacturing process complicated.
According to another aspect of the present invention, there is provided a MOS type semiconductor apparatus, comprising: first main surface and second main surface which face in opposite directions; a first conductivity type drift layer having a high resistivity; a second conductivity type base region formed in a surface layer of the first conductivity type drift layer on the side of the first main surface; a first conductivity type source region that is spaced from the first conductivity type drift layer by the second conductivity type base region; a gate electrode layer formed on a gate insulating film over a surface of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer; a source electrode formed in contact with both of the first conductivity type source region and the second conductivity type base region; a second conductivity type drain layer formed on a surface of the first conductivity type drift layer on the side of the second main surface; a drain electrode formed on the second main surface in contact with the second conductivity type drain layer, and a gate electrode formed in contact with the gate electrode layer, wherein a ballast resistance layer is provided between the first conductivity type drift layer and the second conductivity type drain layer, the ballast resistance layer including a portion having a resistivity in a range of 0.05 to 1 xcexa9xc2x7cm and a thickness in a range of about 30 xcexcm to 80 xcexcm.
In a trench-gate-type IGBT having a trench formed with a depth larger than that of the second conductivity type base region such that the first conductivity type source region is exposed to an inner wall of the trench, too, a ballast resistance layer may be provided between the first conductivity type drift layer and the second conductivity type drain layer, and the ballast resistance layer may include a portion having a resistivity in a range of 0.05 to 1 xcexa9xc2x7cm and a thickness in a range of about 30 xcexcm to 80 xcexcm.
In the above arrangement, the ballast resistance layer is supposed to provide resistance, and serves to disperse current that would otherwise cause avalanche breakdown. If the resistivity of this ballast layer is lower than the above-indicated range, or its thickness is smaller than the above-indicated range, the layer may sufficiently function as a resistor, but may affect other characteristics of the device, for example, may increase the ON-state voltage.
Preferably, the resistivity of the ballast resistance layer is in a range of 0.1 to 0.4 xcexa9xc2x7m. With the resistivity thus controlled, the resulting device operates appropriately, and shows improved capability to withstand avalanche breakdown, due to the function of the ballast layer to disperse large current.
The ballast resistance layer may be of first conductivity type, or may consist of a first conductivity type portion that contacts with the drift layer, and a second conductivity type portion that contact with the drain layer. In either case, the ballast resistance layer provides resistance, and serves to disperse large current.
According to a further aspect of the present invention, a MOS type semiconductor apparatus is provided which comprises: first main surface and second main surface which face in opposite directions, a first conductivity type drift layer having a high resistivity; a second conductivity type base region formed in a surface layer of the first conductivity type drift layer on the side of the first main surface; a first conductivity type source region that is spaced from the first conductivity type drift layer by the second conductivity type base region; a gate electrode layer formed on a gate insulating film over a surface of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer; a source electrode formed in contact with both of the first conductivity type source region and the second conductivity type base region, a first conductivity type drain layer formed on a surface of the first conductivity type drift layer on the side of the second main surface, the first conductivity type drain layer having a smaller resistivity than the first conductivity type drift layer; a drain electrode formed on the second main surface in contact with a surface of the first conductivity type drain layer; and a gate electrode formed in contact with the gate electrode layer, wherein a ballast resistance layer is provided between the first conductivity type drift layer and the first conductivity type drain layer. The ballast resistance layer provides a region that will not be depleted when avalanche breakdown occurs upon application of a high voltage to the MOS type semiconductor device that is placed in an OFF state, and this ballast resistance layer has a resistivity that is substantially equal to or smaller than that of the first conductivity type drift layer, and larger than one-tenth of that of the first conductivity type drift layer, and a thickness that is at least about 1 xcexcm.
In a trench-gate-type IGBT having a trench formed with a depth larger than that of the second conductivity type base region such that the first conductivity type source region is exposed to an inner wall of the trench, too, the first conductivity type ballast resistance layer may be provided between the first conductivity type drift layer and the first conductivity type drain layer. The ballast resistance layer provides a region that will not be depleted when avalanche breakdown occurs upon application of a high voltage to the MOS type semiconductor device that is placed in an OFF state. This ballast resistance layer has a resistivity that is substantially equal to or smaller than that of the first conductivity type drift layer, and larger than one-tenth of that of the first conductivity type drift layer, and a thickness that is at least about 1 xcexcm.
Preferably, the thickness of the portion of the ballast resistance layer is not larger than one half (xc2xd) of that of the first conductivity type drift layer.
In the above arrangement, the ballast resistance layer is supposed to provide resistance, and serve to disperse large current. If the resistivity of this ballast layer is lower than the above-indicated range, or its thickness is smaller than the above-indicated range, the layer may sufficiently function as a resistor, but may affect other characteristics of the device, for example, may increase the ON-state voltage.